Unlike Intel and AMD, VIA uses two distinct development codenames for each of its CPU cores. In this case, the codename 'CN' was used in the U.S. by Centaur Technology. Biblical names are used as codes by VIA in Taiwan, and Isaiah was the choice for this particular processor and architecture. It is expected that the VIA Isaiah is twice as fast in integer performance and four times as fast in floating-point performance as previous-generation VIA Esther at an equivalent clock speed. Power consumption is also expected to be on par with the previous generation VIA CPUs, with Thermal Design Power ranging from 5W to 25W.7 Being a completely new design, the Isaiah architecture was built with support for features like the x86-64 instruction set and x86 virtualization which were unavailable on previous VIA microprocessors such as the C7 line, while retaining the C7 encryption extensions.
Out-of-order and superscalar design: Providing much better performance than its predecessor, the VIA C7 processor, which was in-order. This puts the Isaiah architecture in line with current offerings from AMD and Intel, except for Intel Atom which has an in-order design.
Instructions fusion: Allows to combine some instructions as a single instruction to reduce power requirements and give a higher performance.
Improved branch prediction: Uses eight predictors in two pipeline stages.
Cache design: An exclusive cache design means that contents of the L1 cache is not duplicated in the L2 cache, providing a larger total cache.
Data prefetch: Incorporating new mechanisms for data-prefetch, including both the loading of a special 64-line cache before loading the L2 cache and a direct load to the L1 cache.
Memory access: Merging of smaller stores into larger load data.
Execution units: Seven execution units are available, that allows up to seven micro-ops being executed per clock.
2 Integer units
One unit (ALU1) is feature complete, while the other (ALU2) lacks some low usage instructions and therefore can be used more often for tasks like address calculations.
2 Store units (VIA refer to this as one for Address Store and another for Data Store)
1 Load unit
2 Media units with 128-bit wide datapath, supporting 4 single precision or 2 double-precision operations.
One unit (MEDIA-A) correspond to floating point support, 2-clock latency for single-precision and double-precision add instructions, integer SIMD, encryption, divide and square root.
The other unit (MEDIA-B) performs single-precision multiplies, with 3-clock latency for double-precision multiplies.
Media computation: Refers to the use of floating point execution units.
Using an execution unit for floating point computation and another for multiplication allows the execution of up to four floating point and four multiplies per clock.
A new implementation of FP-addition with the lowest latency (in clocks) seen in x86 processors so far.
Almost all integer SIMD instructions execute in one clock.
.jpg)
